Semiconductor devices, such as semiconductor integrated circuits (ICs), include numerous semiconductor device structures, such as interconnected complementary metal oxide semiconductor (CMOS) transistors (i.e. both P-channel and N-channel MOS transistors). Interconnectivity between various device structures on ICs is accomplished by metallized contacts forming interlayer connections between the device structures. With the increase in the number of semiconductor device structures in ICs, it becomes important to shrink the size of individual device structures and maintain manufacturability.
Semiconductor device structures, such as CMOS transistors, have now been designed to have feature sizes (e.g., gate electrodes) less than or equal to forty-five nanometers in width. However, as the size of semiconductor device structures shrink, the size of the contacts decrease. Reduction in the size of the contacts also reduces the contact area between these contacts and the devices structures, thereby increasing the resistance therebetween.
Accordingly, it is desirable to provide semiconductor devices having reduced contact resistance and a method for fabricating such semiconductor devices. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.